MU0 (6) 썸네일형 리스트형 MUX(멀티플렉서) - VHDL AMUX--------------------------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; Entity AMUX is port(IR_out : in std_logic_vector(7 downto 0); PC_out : in std_logic_vector(7 downto 0); Asel : in std_logic; addr : out std_logic_vector(7 downto 0)); end AMUX; architecture BEHAV of AMUX is.. ALU-산술연산장치 Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; Entity ALU is port(rst : in std_logic; ALUfs : in std_logic_vector(2 downto 0); a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); sum : out std_logic_vector(7 downto 0)); end ALU; Architecture BEHAV of ALU is begin process(rst, ALUfs, a,b) begin if(rst = '1') then sum.. ACC - accumulator(누산기) Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; Entity ACC is port(clk : in std_logic; rst_n : in std_logic; ACCce : in std_logic; sum : in std_logic_vector(7 downto 0); ACC15 : out std_logic; ACCz : out std_logic; a : out std_logic_vector(7 downto 0)); End ACC; Architecture BEHAV of ACC is signal acc_r : std_logic_vector(7 downto 0); beg.. PC-(Program Counter) Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity PC is port(PCce : in std_logic; clk : in std_logic; rst_n : in std_logic; sum : in std_logic_vector(7 downto 0); pc_out : out std_logic_vector(7 downto 0)); end PC; architecture BEHAV of PC is begin process(clk, rst_n, Pcce) begin if(rst_n = '0')then pc_out '0'); elsif(clk ='0' and cl.. IR(Instruction Register)-VHDL( 명령어레지스터) Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity IR is port( rst_n : in std_logic; clk : in std_logic; irce : in std_logic; data : in std_logic_vector(7 downto 0); ir_out : out std_logic_vector(7 downto 0); opcode : out std_logic_vector(3 downto 0)); end IR; architecture BEHAV of IR is signal ir_r : std_logic_vector(7 downto 0); beg.. MU0 Control Unit(한국항공대 09년도 디지털논리실험 프로젝트) 위의 표의 상태에 맞추어 VHDL 코딩을 하도록 합니다. Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity controlunit is port(Opcode : in std_logic_vector (3 downto 0); Reset : in std_logic; ExftI : in std_logic; ACCz : in std_logic; ACC15 : in std_logic; Asel : out std_logic; Bsel : out std_logic; ACCce : out std_logic; PCce : out std_logic; IRce : out std.. 이전 1 다음