위의 표의 상태에 맞추어 VHDL 코딩을 하도록 합니다.
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity controlunit is
port(Opcode : in std_logic_vector (3 downto 0);
Reset : in std_logic;
ExftI : in std_logic;
ACCz : in std_logic;
ACC15 : in std_logic;
Asel : out std_logic;
Bsel : out std_logic;
ACCce : out std_logic;
PCce : out std_logic;
IRce : out std_logic;
ACCoe : out std_logic;
ALUfs : out std_logic_vector (2 downto 0);
MEMrq : out std_logic;
RnW : out std_logic;
ExftO : out std_logic);
end controlunit;
architecture Beh of controlunit is
type StateType is(RST, LDA, STO, ADD, SUB, JMP, JGE, JNE, STP);
signal present : StateType;
signal Idata : std_logic_vector(7 downto 0);
signal Odata : std_logic_vector(11 downto 0);
begin
Idata <= Opcode & Reset & ExftI & ACCz & ACC15;
process(Reset, Idata)
begin
if(Reset = '1') then
Odata <= "001110000110";
present <= RST;
else
if(Idata(7 downto 3) = "00000") then
present <= LDA;
if(Idata(2) = '0') then
Odata <= "111000000111";
else
Odata <= "000110100110";
end if;
elsif(Idata(7 downto 3) = "00010") then
present <= STO;
if(Idata(2) = '0') then
Odata(11 downto 6) <= "100001";
Odata(2 downto 0) <= "101";
else
Odata <= "000110100110";
end if;
elsif(Idata(7 downto 3) = "00100") then
present <= ADD;
if(Idata(2) = '0') then
Odata <= "111000010111";
else
Odata <= "000110100110";
end if;
elsif(Idata(7 downto 3) = "00110") then
present <= SUB;
if(Idata(2) = '0') then
Odata <= "111000111111";
else
Odata <= "000110100100";
end if;
elsif(Idata(7 downto 3) = "01000") then
present <= JMP;
Odata <= "100110100110";
elsif(Idata(7 downto 3) = "01010") then
present <= JGE;
if(Idata(0) = '0') then
Odata <= "100110100110";
else
Odata <= "000110100110";
end if;
elsif(Idata(7 downto 3) = "01100") then
present <= JNE;
if(Idata(1) = '0') then
Odata <= "100110100110";
else
Odata <= "000110100110";
end if;
elsif(Idata(7 downto 3) = "01110") then
present <= STP;
Odata <= "100000000010";
end if;
end if;
end process;
Asel <= Odata(11);
Bsel <= Odata(10);
ACCce <= Odata(9);
PCce <= Odata(8);
IRce <= Odata(7);
ACCoe <= Odata(6);
ALUfs <= Odata(5 downto 3);
MEMrq <= Odata(2);
RnW <= Odata(1);
ExftO <= Odata(0);
end Beh;
