Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity IR is
port( rst_n : in std_logic;
clk : in std_logic;
irce : in std_logic;
data : in std_logic_vector(7 downto 0);
ir_out : out std_logic_vector(7 downto 0);
opcode : out std_logic_vector(3 downto 0));
end IR;
architecture BEHAV of IR is
signal ir_r : std_logic_vector(7 downto 0);
begin
process(clk, rst_n, irce)
begin
if(rst_n = '0') then
ir_r <= (others => '0');
elsif(clk = '0' and clk'event)then
if irce = '1' then
ir_r <= data(7 downto 0);
end if;
end if;
end process;
ir_out <= ir_r;
opcode <= ir_r(7 downto 4);
end BEHAV;
한국항공대 09 디지털논리실험 프로젝트