Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity ACC is
port(clk : in std_logic;
rst_n : in std_logic;
ACCce : in std_logic;
sum : in std_logic_vector(7 downto 0);
ACC15 : out std_logic;
ACCz : out std_logic;
a : out std_logic_vector(7 downto 0));
End ACC;
Architecture BEHAV of ACC is
signal acc_r : std_logic_vector(7 downto 0);
begin
process(clk, rst_n, ACCce)
begin
if(rst_n = '0') then
acc_r <= (others => '0');
elsif (clk = '0' and clk'event) then
if(ACCce = '1')then
acc_r <= sum;
end if;
end if;
a <= acc_r;
end process;
ACC15 <= acc_r(7);
ACCz <= '1' when acc_r = "00000000" else '0';
end BEHAV;
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