Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity ALU is
port(rst : in std_logic;
ALUfs : in std_logic_vector(2 downto 0);
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
sum : out std_logic_vector(7 downto 0));
end ALU;
Architecture BEHAV of ALU is
begin
process(rst, ALUfs, a,b)
begin
if(rst = '1') then
sum <= (others => '0');
else
case ALUfs is
when "000" => sum <= b;
when "100" => sum <= b+1;
when "010" => sum <= a+b;
when "111" => sum <= a-b;
when others => sum <= "00000000";
end case;
end if;
end process;
end BEHAV;
