MUX(멀티플렉서) - VHDL

AMUX---------------------------------------------------------------------------------

Library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

Entity AMUX is

port(IR_out : in std_logic_vector(7 downto 0);

PC_out : in std_logic_vector(7 downto 0);

Asel : in std_logic;

addr : out std_logic_vector(7 downto 0));

end AMUX;

architecture BEHAV of AMUX is

begin

addr <= PC_out when asel = '0' else "0000" & IR_out(3 downto 0);

end BEHAV;

BMUX---------------------------------------------------------------------------------

Library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

Entity BMUX is

port(data : in std_logic_vector(7 downto 0);

addr : in std_logic_vector(7 downto 0);

Bsel : in std_logic;

b : out std_logic_vector(7 downto 0));

end BMUX;

architecture BEHAV of BMUX is

begin

b <= addr when bsel = '0' else data;

end BEHAV;