IR (1) 썸네일형 리스트형 IR(Instruction Register)-VHDL( 명령어레지스터) Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity IR is port( rst_n : in std_logic; clk : in std_logic; irce : in std_logic; data : in std_logic_vector(7 downto 0); ir_out : out std_logic_vector(7 downto 0); opcode : out std_logic_vector(3 downto 0)); end IR; architecture BEHAV of IR is signal ir_r : std_logic_vector(7 downto 0); beg.. 이전 1 다음