down counter (1) 썸네일형 리스트형 [디지털논리실험]VHDL 다운카운터(5비트 20진) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt_20 is port(reset,clk:in std_logic; res:out std_logic_vector(4 downto 0)); end cnt_20; architecture logic of cnt_20 is signal tmp:std_logic_vector(4 downto 0); begin process(clk, reset) begin if(reset='1') then tmp 이전 1 다음